A typical optical receiver includes at least one photodiode that detects an optical data signal and converts it into an electrical current signal, at least one transimpedance amplifier (TIA) that converts the electrical current signal into an electrical voltage signal and CDR circuitry that processes the electrical voltage signal to recover the clock and then uses the recovered clock to sample the data in order to recover the data. Typical CDR circuitry includes a phase-locked loop that phase-aligns a local reference clock with transitions in the incoming data signal and then uses the phase-aligned reference clock to sample the incoming data signal.
In the optical communications industry, efforts are continuously being made to increase data rates. As data rates are increased, standards committees in the optical communications industry set standards that govern the mechanical and electrical designs on optical communications modules. In addition to formal standards, multi-source agreements (MSAs) are entered into among multiple manufacturers for providing de facto standards for making products that are compatible across vendors. One such committee is the Small Form Factor (SFF) Committee.
Small form factor pluggable (SFP) optical transceiver modules have a form factor and electrical interface that are specified by an MSA under the auspices of the SFF Committee. An MSA known as SFF 8419 is a 32 Gigahertz (GHz) standard that requires that newly manufactured SFP optical transceiver modules be backwards compatible with modules that operate at 16 GHz and 8 GHz data rates. Because of the backwards compatibility requirement, the newer modules are required by the MSA to meet the same form factor and electrical interface standards specified for the earlier modules. The specified electrical interface provides a single rate select bit communicated over a single input/output (I/O) pin to indicate whether the incoming data signal is a 32 GHz signal or is other than a 32 GHz signal. If the rate select bit is high, this indicates that the incoming data signal is a 32 GHz signal. If the rate select bit is low, this indicates that the incoming data signal is other than a 32 GHz signal. Thus, when the rate select bit is low, it is left up to the module to determine whether the incoming data signal is an 8 GHz signal or a 16 GHz signal and to frequency and phase lock onto the incoming data signal within a specified time frame. The process of determining the data rate of the incoming data signal and of frequency and phase locking onto the incoming data signal within a specified time frame is referred to hereinafter as automatic rate negotiation. A need exists for a CDR that is capable of performing automatic rate negotiation.